Innosilicon’s IP portfolio includes a wide range of advanced high-speed interface subsystems. The key IP Trio for Next Gen AI, such as LPDDR6/5X Combo, GDDR7/6X, MR DDR5, UCIe Chiplet, UALINK, PCIe ...

Xiphera Ltd and iWave Global have entered into a collaboration to combine Xiphera’s advanced cryptographic solutions with iWave’s extensive portfolio of Altera FPGA-based boards and solutions.

Pete Bernard, CEO, EDGE AI FOUNDATION, said: “ The EDGE AI FOUNDATION is dedicated to building a dynamic ecosystem that makes intelligent systems more capable, efficient, and sustainable. We are ...

Synopsys is different. With the industry’s most comprehensive and adaptable Foundation IP portfolio, a world-class R&D engine ...

As TSMC’s 2nm mass production countdown begins, speculation mounts over its major clients. KLA, a key chipmaking equipment supplier, reports that around 15 customers are designing at the N2 node, ...

According to the latest memory semiconductor figures released by market research firm Counterpoint Research on Sept. 24, SK hynix led the HBM market in the second quarter with a 62% market share.

OpenAI and NVIDIA today announced a letter of intent for a landmark strategic partnership to deploy at least 10 gigawatts of NVIDIA systems for OpenAI's next-generation AI infrastructure to train and ...

In the article, CEO Jaehong Park not only introduces Eagle-N, but also shares insights on the broader industry landscape and BOS’s vision to shape the future of automotive AI. From cutting-edge NPU ...

But to make use of those technologies, the firms that design chips are increasingly relying on AI-powered software from providers such as Cadence Design Systems (CDNS.O) and Synopsys , both of which ...

NanoEdge AI Studio v5 is the first AutoML tool for STM32 microcontrollers capable of generating anomaly data out of typical logs, thanks to a new feature we call Synthetic Data Generation.

It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected,” Gordon Moore wrote in his famous article, Cramming more ...

Breakthrough Gen3 UCIe IP subsystem achieves 64 Gbps per-I/O pin data rates and doubles shoreline bandwidth density, enabling scalable XPUs, and data center chiplet architectures with TSMC's 3nm ...