September 20th, 2005 – The Intellectual Property (IP) provider - Digital Core Design (DCD) today has announced the release of the DSPI_FIFO and DSPIS IP Cores. The DSPI_FIFO and DSPIS IP Cores ...

This paper describes the development of a configurable SoC platform using configurable IP cores, which is designed for low cost, low power and targeted for Bluetooth® and ULP (Ultra Low Power) ...

In his most recent column, “A SPIFI new idea,” Jack Gannsle expresses his pleasure in the capabilities of a new flash memory interface from ST Microelectronics, which uses a Serial Peripheral ...

The 23LCV1024 is a 1 Mbit Serial Peripheral Interface (SPI) serial SRAM with battery backup and SDI interface. The memory of the device is accessed via a simple SPI compatible serial bus. The bus ...

The Golden Gate family of serial peripheral interface bridge processors provides a means to connect PCI and PCI-X buses to the SPI3 and SPI4.2 high-speed serial network interfaces. The processors ...

Robust serial interfaces such as USB and IEEE-1394 ™ have revolutionized personal computing. They provide a simple-to-use interconnection to a variety of different peripherals, ranging from products ...

Serial buses dot the landscape of embedded design. From displays to storage to peripherals, serial interfaces make communications possible. Many serial communication interfaces compete for use in ...