EDN

Xilinx ISE 12 adds intelligent clock gating

SAN FRANCISCO—Xilinx Inc. Monday (May 3) introduced a new version of its ISE Design Suite to support its Virtex-6 and Spartan-6 FPGA families. According to the company, ISE 12 adds intelligent clock ...
Design-Reuse

Xilinx Releases ISE WebPACK 8.2i - FPGA Industry's Only Free Fully Featured Design Suite

SAN JOSE, Calif. -- July 17, 2006-- Xilinx, Inc. today announced the immediate availability of the Integrated Software Environment (ISE(TM)) WebPACK(TM) 8.2i release -- the latest version of the ...
Design-Reuse

Xilinx Announces ISE WebPACK 9.1i Release - Delivering Highest System Performance and Fastest Compile Time

Free downloadable design suite for both Windows and Linux delivers on average 10% lower dynamic power, and expanded FPGA device support January 22, 2007, SAN JOSE, Calif. – Xilinx, Inc. (NASDAQ: ...
EDN

The Interview: Wim Roelandts, Xilinx CEO, sticks to FPGA basics

MUNICH — Although in 2001 FPGA vendor Xilinx was briefly caught in the down-draught of the communications bust it has generally managed to turn in better financial numbers than most of its ASIC rivals ...