EDN

Renesas memory cell mixes SRAM, DRAM tech

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...
EDN

Renesas halves memory chip size by merging SRAM and DRAM

TOKYO — Renesas Technology Corp. has developed a new SRAM memory cell combining SRAM and DRAM technologies. The new cell is about half the size of conventional SRAM cells but retains such advantages ...
Semiconductor Engineering

The Uncertain Future Of In-Memory Compute

Experts at the Table — Part 2: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, chief technology officer at Alphawave Semi; Steve Roddy, chief ...
Semiconductor Engineering

Mixed SRAM And eDRAM Cell For Area And Energy-Efficient On-Chip AI Memory (Yale Univ.)

“AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption.
Forbes

d-Matrix Emerges From Stealth With Strong AI Performance And Efficiency

Startup launches “Corsair” AI platform with Digital In-Memory Computing, using on-chip SRAM memory that can produce 30,000 tokens/second at 2 ms/token latency for Llama3 70B in a single rack. Using ...
Nasdaq

MoSys Launches New QUAZAR QPR Family of Low Cost, Quad Partition Rate SRAM Memory ICs Targeted for Accelerating INTEL and XILINX FPGA Designs

QDR Level Performance - Replaces up to 8X QDRs - Capacities of 576Mb or 1Gb in Single Device Costing Less Than $200 in Volume Quantities SAN JOSE, CA / ACCESSWIRE / July 15, 2020 / MoSys, Inc. (NASDAQ ...
Electronic Design

Use 1TRAM Blocks To Embed More Memory On Logic Chips

Data refresh and cell-layout issues must be addressed to optimally implement this space-saving alternative to SRAM technology. As the system-on-a-chip (SoC) era marches forward, there's a pressing ...