EDN

The pitfalls of mixing formal and simulation: Where trouble starts

The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under ...
Digi Times

Altair expands EDA footprint, offering diverse system-level verification and simulation tools

The application of artificial intelligence (AI) has emerged as a driving force behind global technological innovation. As AI adoption proliferates, the mastery of semiconductor chip technology becomes ...
Semiconductor Engineering

Engineering After Orthogonalization: Why Verification Has Become A Lifecycle Discipline

Today, teams often rely on disconnected logs, postmortems, and ad-hoc debug when failures emerge in the field. Lifecycle ...
Semiconductor Engineering

Cloud-Ready Circuit Simulation Accelerates SoC Verification

Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, ...
Design-Reuse

Lattice and Aldec Announce New Alliance For FPGA Design And Verification

Simulator Delivers Industry Leading Speed, and is the Only OEM Mixed Language Simulator for FPGA Design HILLSBORO, OR - April 21, 2008 - Lattice Semiconductor Corporation (NASDAQ: LSCC) and Aldec, ...
Business Wire

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMe TM SSD and PCIe® designs using ...
EDN

TLM-Driven Design and Verification using Cadence®

Transaction level modeling (TLM) is gaining favor over register-transfer level (RTL) for design components because of its many advantages—including faster design and verification times, easier ...
Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
it.tmcnet

Cadence Intros Verification Solution with Integrated Formal Analysis and Simulation Capabilities

Cadence Design Systems, which provides electronic design solutions, announced Cadence Incisive Enterprise Verifier, an integrated verification solution delivering dual power of formal analysis and ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

AV Transformation Design and Verification Turbocharges OEMs

Autonomous vehicles are ushering in a new era of self-driving cars, taxis, trucks, and a host of other means of transport, which is having an enormous impact upon the fortunes of vehicle manufacturers ...