EDN

The practicing instrumentation engineer’s guide to the DFT – Part 1: Understand DFT and FFT implementations

There are many books and articles on the Fourier Transform and its implementation available. A quick survey of these resources shows that they are not geared to the needs of the “Practicing ...
EDN

Moving DFT into chip design with hardware emulation

Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will ...
Semiconductor Engineering

Signal Connectivity Checks Are Not Just For Design-For-Test Teams

The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are ...
Semiconductor Engineering

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...
Electronic Design

DFT that gets AI chips to market faster

As the demand for processing power for artificial intelligence (AI) applications grows, semiconductor companies are racing to develop AI-specific silicon. The AI market is incredibly dynamic, with ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...
Design-Reuse

Smart Chips, Safe Trips: How DFT Powers the Future of Autonomy with Vijayaprabhuvel Rajavel

In a significant step toward restoring America’s semiconductor leadership, the U.S. Department of Commerce has announced $1.4 billion in new awards under the CHIPS National Advanced Packaging ...